The prior art shows that a field effect transistor (FET) can be built to control current passing between its source and drain regions by means of an electric field which results from the imposition of a voltage on the transistor gate. Such transistors are finding widespread use, especially in integrated circuits.
An insulated gate FET (IGFET) is typically created by implanting source and drain regions in a substrate material, the substrate being of one conductivity type and the source and drain regions being of another conductivity type. The electric fields in the channel, which is situated between the source and between the source and drain regions, result from the superposition of two separate electric fields. One electric field is due to the voltage applied between the gate and the substrate and is directed primarily perpendicularly to the substrate surface. This field gives rise to the channel at the substrate surface. The second electric field is created by a voltage potential between the drain and source regions. The second field causes charge carriers to flow from the source to the drain along the channel. The resulting electric field, which affects the performance of an IGFET, also depends upon the material conductivity types chosen and any doping of the channel region by impurities. One of the most popular IGFET configurations (the npn metal-oxide semiconductor FET, or MOSFET) is made by implanting n+- type source and drain regions in a p+- type substrate and using an oxide, such as silicon dioxide, as the gate insulator. In operation, the drain region of this configuration is held at a positive voltage with respect to its source region. This drain-to-source voltage creates depletion regions surrounding the source and drain regions, with the depletion region around the drain being somewhat larger.
In the absence of any channel doping, npn MOSFETS are "normally off" devices. That is, npn MOSFETS do not conduct a current until a sufficiently positive voltage (depending upon the materials used) is imposed between the gate and the source region. When the gate voltage exceeds this device-dependent threshold voltage, current begins to flow between the device's source and drain.
In today's electronic technology, where it is desirable to realize an increasing number of functions on an integrated circuit, increased transistor density is desirable. One manner of increasing transistor density is to decrease the physical size of each individual MOSFET. This size diminishment includes a shortening of the channel length, i.e., the separation between source and drain regions. Shortening the MOSFET channel length increases the electric field strength within the channel resulting from the drain-to-source voltage. This increased field strength has its disadvantages.
One major disadvantage of the short channel MOSFET is that high electric fields caused by the drain-to-source voltage imposed across the short channel can create a current flowing in the substrate below the MOSFET channel region. The drain-to-source voltage level at which this current is established is termed the "punch-through" voltage. Because the punch-through effect limits the peak operating voltage of the device (i.e., the voltage imposed between the source and drain regions), it is desirable to render the device as resistant to the occurrence of punch-through current as possible or, stated another way, to design the device so that punch-through current occurs only at a voltage which is well above the drain-to-source voltages at which the device will be operated.
The most commonly used methods for increasing the punch-through voltage are to increase the impurity concentration in the substrate and to increase the channel length. Increased impurity concentration results in lower carrier mobilities, adversely affecting the MOSFET's switching speed. A longer channel increases the area covered by each individual MOSFET and also adversely affects MOSFET switching speed.
One approach to increase the punch-through voltage is to place an insulating barrier in the substrate material where it will reduce the strength of the subsurface electric fields. As disclosed in Konaka et al., U.S. Pat. No. 4,523,213, some increase in the punch-through voltage can be obtained by placing this insulating barrier below the plane connecting the lower surfaces of the implanted source and drain regions. This placement, however, will not prevent a current from being generated in the channel region above the plane connecting the lower surfaces of the source and drain regions. It is desirable, therefore, to have a MOSFET structure which increases the punch-through voltage beyond the levels possible with the structures known to the prior art.